Internship Generic correctness of iterative cirtical software architecture exploration-Saclay-H/F

CEA · Saclay (91) · Stage

Publiée le 24 octobre 2026

Subject

The internship aims to establish the correctness of the iterative exploration of critical embedded software architectures, whatever the clustering strategy applied.

Job description

As an intern at the CEA, you will have the opportunity to work within a world-renowned research environment. Our teams consist of passionate and dedicated experts, providing an ideal setting for learning and collaboration. You will have access to state-of-the-art equipment and top-tier research resources to carry out your assignments. The work conducted may potentially lead to a scientific publication.

Context :

The QuaRTOS-DSE tool explores the design space of a critical application by applying, in sequence, strategies that group its functions into tasks, each producing an architecture Mi+1 from Mi. Recent work (VECoS 2026) defines preservation properties that every correct reclustering must satisfy, checked with TLA+ and the TLC model checker: conservation of the configuration, correspondence of the executions per function and per task, and preservation of the communication. It was extended to partitioned multicore deployments and to the coherence of the data each function reads.

These properties are necessary but not sufficient: a reclustering can satisfy all of them without preserving the behavior of the system. Each architecture is compared only with the one it came from, with no guarantee that the verdicts compose along an exploration. Finally, the multicore model assumes that each task stays on its core, and ignores interference from shared hardware resources.

The internship aims to remove these three limitations.

What do we expect from you?

Study the existing work: the formal model of QuaRTOS-DSE, the preservation properties and their TLA+ models,

Complete the necessary equivalence properties between two architectures with new properties, to reach a sufficient condition,

Propose a solution or a proof for the coverage of the properties with respect to the iterative exploration: establish under which conditions Mi ≈ Mi+1 ≈ … ≈ Mk implies Mi ≈ Mk,

Extend the multicore model to account for task migration between cores and interference from shared hardware resources,

Evaluate the proposals on existing use cases, including an industrial protection relay, and measure their verification cost.

During this internship, the student will gain practical experience with safety-critical systems and formal verification techniques, in particular model checking.

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Methods / Means: TLA+/TLC, Python, EMF/xtext

Level required: Master's degree, Bac+5 - Master of Science

Duration: 6 months

Skills: Understanding of critical embedded and real-time software; knowledge of formal methods (temporal logic, model checking) is expected. Fluent English, teamwork, curiosity

~1400€ monthly "salary", depending on whether the intern has a scholarship or not.

In line with CEA's commitment to integrating people with disabilities, this job is open to all.

Location: Site Saclay, France, Ile-de-France, Essonne (91), Palaiseau

Start date: to be defined

Contact: […], […]

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Applicant Profile

Master's degree, Bac+5 - Master of Science

Understanding of critical embedded and real-time software; knowledge of formal methods (temporal logic, model checking) is expected. Fluent English, teamwork, curiosity

Description de l'unité

Within the CEA List, the Electronics Design Automation and Architectures Laboratory (LECA) has the mission to design innovative and flexible system-on-chip architectures that meet the challenges of performance, cost, energy consumption, safety and security, targeting critical embedded systems and HW accelerators for embedded AI. To reduce the development time and improve the quality of these architectures, the team of experts develop innovative design tools and methods.

Compétences

Voir l'offre d'origine et postuler · Source : site carrières de CEA

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